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L6731B
Adjustable step-down controller with synchronous rectification Dedicated to DDR Memory
Features

Input voltage range from 1.8V to 14V Supply voltage range from 4.5V to 14V Adjustable output voltage down to 0.6V with 0.8% accuracy over line voltage and temperature (0C~125C) Fixed frequency voltage mode control TON lower than 100ns 0% to 100% duty cycle VDDR input sense Regulates VTT and VTTREF within 1% of VDDQ Soft-start and inhibit High current embedded drivers Predictive anti-cross conduction control Programmable high-side and low-side RDS(on) sense over-current-protection Selectable switching frequency 250KHz/ 500KHz Power good output Sink/source capability for ddr memory and termination supply Over voltage protection Thermal shut-down Package: HTSSOP16 HTSSOP16 (Exposed Pad)

Applications

High performance / high density DC-DC modules Low voltage distributed DC-DC niPOL converters DDR memory supply DDR termination supply Graphic cards
Order Codes
Part number L6731B L6731BTR June 2006 Package HTSSOP16 HTSSOP16 Rev 3 Packing Tube Tape & Reel 1/24
www.st.com 24
Contents
L6731B
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4 5
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 11 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 6.3 6.4 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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L6731B
Summary description
1
Summary description
The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600mV with a maximum tolerance of 0.8%. If an external reference is used, it will be trasferred divided by 2 to the N.I. input of the error-amplifier, in accordance to the DDR memory specifications. An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1% on both Vtt and Vttref. It's possibile to provide an external reference from 0V to 2.5V in order to meet the specification for DDRI and DDRII. The input voltage can range from 1.8V to 14V, while the supply voltage can range from 4.5V to 14V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The PWM duty cycle can range from 0% to 100% with a minimum on-time (TON, MIN) lower than 100ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250KHz or 500KHz). The error amplifier features a 10MHz gain-bandwidth-product and 5V/s slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(on) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. The converter can always sink current. Other features are Power-Good, not latched over-voltage-protection, feedback disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters.
3/24
Summary description
L6731B
1.1
Figure 1.
Functional description
Block Diagram
VCC=4.5V to14V
Vin=1.8V to14V
OCL
OCH VCC
VCCDR
BOOT
LDO
SS/INH
Monitor Protection and Ref
OSC
-
HGATE
Vo
PHASE
DDR-IN R
L6731B
LGATE
R PGOOD
+ -
0.6V
+
PWM
PGND
+
+ -
E/A
SGND
VFB VTTREF COMP
4/24
L6731B
Electrical data
2
2.1
Table 1.
Electrical data
Maximum rating
Absolute maximum ratings
Parameter VCC to GND and PGND, OCH, PGOOD Value -0.3 to 18 0 to 6 0 to VBOOT - VPHASE BOOT PHASE VPHASE PHASE Spike, transient < 50ns (FSW = 500KHz) SS, FB, VTTREF, DDR-IN, SYNC, OCL, LGATE, COMP, VCCDR OCH Pin PGOOD Pin OTHER PINS Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002 "Human Body Model" Acceptance Criteria: "Normal Performance" -0.3 to 24 -1 to 18 -3 +24 -0.3 to 6 1500 1000 2000 V V V Unit V V V V Symbol VCC
VBOOT - VPHASE Boot Voltage VHGATE - VPHASE VBOOT
2.2
Table 2.
Thermal data
Thermal data
Description Thermal Resistance Junction to ambient Storage temperature range Junction operating temperature range Ambient operating temperature range Value 50 -40 to 150 -40 to 125 -40 to +85 Unit C/W C C C
Symbol RthJA(1) TSTG TJ TA
1. Package mounted on demoboard
5/24
Pin connections and functions
L6731B
3
Figure 2.
Pin connections and functions
Pins connection ( Top view)
PGOOD VTTREF
1 2 3 4
5
16 15 14 13 12 11 10 9
VCC VCCDR LGATE PGND BOOT HGATE PHASE
SGND
FB COMP SS/INH DDR-IN
6 7 8
OCL
OCH
HTSSOP16
Table 3.
Pin n.
Pin functions
Name Function This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to VCCDR with a 10K resistor to obtain a logical signal. This pin is connected to the output of an internal buffer that provides 1/2 of DDR-IN. This pin can be connected to the VTTREF input of the DDR memory itself. Filter to GND with 10nF capacitor. All the internal references are referred to this pin. This pin is connected to the error amplifier inverting input. Connect it to VOUT through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10A through the capacitor. When the voltage at this pin is lower than 0.5V the device is disabled. By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency: VEAREF 0-80% of VCCDR -> External Reference/FSW=250KHz
1
PGOOD
2 3 4
VTTREF SGND FB
5
COMP
6
SS/INH
7
DDR-IN
VEAREF = 80%-95% of VCCDR -> VREF = 0.6V/FSW=500KHz VEAREF = 95%-100% of VCCDR -> VREF = 0.6V/FSW=250KHz An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold.
6/24
L6731B
Table 3. Pin functions
Pin connections and functions
A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100A (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation: 8 OCL I OCL * I OCL I VALLEY = -------------------------------2 * R DSONLS Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a "clean" GND. A resistor connected from this pin and the high-side MOSFET(s) drain sets the peakcurrent-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100A current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The over-current threshold is given by the following equation: I OCH * R OCH I PEAK = --------------------------------R DSONHS 10 11 12 13 14 15 16 PHASE HGATE BOOT PGND LGATE VCCDR VCC This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. This pin is connected to the high-side MOSFET(s) gate. Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. This pin is connected to the low-side MOSFET(s) gate. 5V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1F ceramic cap. Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.
9
OCH
7/24
Electrical characteristics
L6731B
4
Electrical characteristics
VCC = 12V, TA = 25C unless otherwise specified.
Table 4.
Symbol
Electrical Characteristics
Parameter Test Condition Min. Typ. Max. Unit
VCC SUPPLY CURRENT VCC Stand By current ICC VCC quiescent current OSC = open; SS to GND OSC= open; HG = open, LG = open, PH=open 7 8.5 9 mA 10
Power-ON VCC Turn-ON VCC threshold Turn-OFF VCC threshold VIN OK VIN OK Turn-ON VOCH threshold Turn-OFF VOCH threshold VOCH = 1.7V VOCH = 1.7V 4.0 3.6 1.1 0.9 4.2 3.8 1.25 1.05 4.4 4.0 1.47 1.27 V V V V
VCCDR Regulation VCCDR voltage Soft Start and Inhibit ISS Oscillator fOSC VOSC 237 Accuracy 450 Ramp Amplitude 500 2.1 550 KHz V 250 263 KHz SS = 2V Soft Start Current SS = 0 to 0.5V 20 30 45 7 10 13 A VCC =5.5V to 14V IDR = 1mA to 100mA 4.5 5 5.5 V
Output Voltage VFB Output Voltage VDIS = 0 to Vth 0.597 0.6 0.603 V
8/24
L6731B
Table 4.
Symbol Error Amplifier REAREF IFB Ext Ref Clamp VOFFSET GV GBWP SR Gate Drivers RHGATE_ON High Side Source Resistance VBOOT - VPHASE = 5V VBOOT - VPHASE = 5V VCCDR = 5V VCCDR = 5V Error amplifier offset Open Loop Voltage Gain Gain-Bandwidth Product Slew-Rate Vref = 0.6V Guaranteed by design Guaranteed by design COMP = 10pF Guaranteed by design EAREF Input Resistance I.I. bias current Vs. GND VF = 0V 2.3 -5 70
Electrical characteristics
Electrical Characteristics
Parameter Test Condition Min. Typ. Max. Unit
100 0.290
150 0.5
k A V
+5 100 10 5
mV dB MHz V/s
1.7 1.12 1.15 0.6

RHGATE_OFF High Side Sink Resistance RLGATE_ON Low Side Source Resistance
RLGATE_OFF Low Side Sink Resistance Protections IOCH IOCL OCH Current Source OCL Current Source
VOCH = 1.7V
90 90
100 100 120
110 110
% %
VFB Rising OVP Over Voltage Trip (VFB / VEAREF) VEAREF = 0.6V VFB Falling VEAREF = 0.6V Power Good Upper Threshold (VFB / VEAREF) Lower Threshold (VFB / VEAREF) VPGOOD PGOOD Voltage Low VFB Rising 108
117
110
112
% %
VFB Falling IPGOOD = -5mA
88
90 0.5
92
Table 5.
Symbol
Thermal Characteristics (VCC = 12V)
Parameter Test Condition Min. Typ. Max. Unit
Output Voltage VFB Output Voltage TJ = 0C~ 125C TJ = -40C~ 125C 0.596 0.593 0.6 0.6 0.605 V 0.605
9/24
Device description
L6731B
5
5.1
Device description
Oscillator
The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper voltage at the EAREF pin (see Table 3. Pins function and section 4.3 Internal and external reference).
5.2
Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5V) is the VCCDR pin (Figure 3.).
Figure 3.
LDO block diagram.
4.5V/14V
LDO
The LDO can be by-passed, providing directly a 5V voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in Figure 4. VCCDR pin must be filtered with at least 1F capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for PGOOD pin (see Table 3. Pins Function).
10/24
L6731B
Device description
5.3
Bypassing the LDO to avoid the voltage drop with low Vcc
If VCC 5V the internal LDO works in dropout with an output resistance of about 1 The . maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to avoid this the LDO can be bypassed.
Figure 4.
Bypassing the LDO
5.4
Internal and external references
It is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the DDR-IN pin. The maximum value of the external reference is 2.5V (typ.):

VEAREF from 0% to 80% of VCCDR -> External reference/FSW = 250KHz VEAREF from 80% to 95% of VCCDR -> VREF = 0.6V/FSW=500KHz VEAREF from 95% to 100% of VCCDR -> VREF = 0.6V/FSW=250KHz
Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered:

The minimum OVP threshold is set at 300mV; The under-voltage-protection doesn't work; The PGOOD signal remains low;
To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into the device (see Figure 5.). Finally it must be taken into account that the voltage at the DDR-IN pin is captured by the device at the start-up when VCC is about 4V.
11/24
Device description
L6731B
5.5
Figure 5.
Error amplifier
Error Amplifier Reference
VCCDR
0.6V/500KHz
DDR-IN 100K 2.5V
0.6V/250KHz DDR-IN/2 250KHz
Error Amplifier Ref.
5.6
Soft start
When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35A and charges the capacitor up to 0.5V. After that it becomes 10A until the final charge value of approximately 4V (see Figure 6.).
Figure 6.
Device start-up: Voltage at the SS pin.
Vc c V in 4V .2 15 .2 V
VCC VIN
Vs s
t
4 V
0V .5
t
12/24
L6731B
Device description
The output of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value. No switching activity is observable if VSS is lower than 0.5V and both MOSFETs are off. When Vss is between 0.5V and 1.1V the low-side MOSFET is turned on because the comp signal is lower than the valley of the triangular wave and so the duty-cycle is 0%. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) even the high-side MOSFET begins to switch and the output voltage starts to increase. The L6731B can always sink or source current. If an over current is detected during the soft-start phase, the device provides a constant-current-protection. In this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and so, in case of high ripple current during the soft-start, the converter can start in any case, limiting the current (see 5.8: Monitoring and protections) but not entering in HICCUP mode. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
5.7
Driver section
The high-side and low-side drivers allow using different types of power MOSFETs (also multiple MOSFETs to reduce the RDS(on)), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration in the range of 20ns. The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control doesn't work when the high-side body diode is conducting because the phase node doesn't go negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates.
13/24
Device description
L6731B
5.8
Monitoring and protections
The output voltage is monitored by means of pin FB. If it is not within 10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The device provides overvoltage-protection: when the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference, the low-side driver is turned on as long as the over voltage is detected (see Figure 7.).
Figure 7.
OVP
LGate
FB
It must be taken into account that there is an electrical network between the output terminal and the FB pin and therefore the voltage at the pin is not a perfect replica of the output voltage. However due to the fact that the converter can sink current, in the most of cases the low-side will turn-on before the output voltage exceeds the over-voltage threshold, because the error amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the behavior is the same, because the low-side is turned-on immediately. The following figure shows the device behavior during an over-voltage event. The output voltage rises with a slope of 100mV/s, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause.
14/24
L6731B
Device description
Figure 8.
OVP: the low-side MOSFET is turned-on in advance.
VOUT 109% VFB
LGate
The device realizes the over-current-protection (OCP) sensing the current both on the highside MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 3. Pins function):

Peak Current Limit Valley Current Limit
The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after a masking time of about 100ns. The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a masking time of about 400ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode: the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10A and when the voltage at the SS pin reaches 0.5V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned off (after the masking time and the internal delay) and returned on at the next pwm cycle. The limit of this protection is that the TON can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned on until the current is over the valleycurrent-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula:
I MAX = IVALLEY +
Vin - Vout TON , MIN L
In constant current protection a current control loop limits the value of the error amplifier output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 9. shows the behaviour of the device during an over current condition that persists also in the soft-start phase.
15/24
Device description
L6731B
5.9
Figure 9.
HICCUP mode during an OCP
Constant current and Hiccup Mode during an OCP. VSS
VCOMP
IL
5.10
Thermal shutdown
When the junction temperature reaches 150C 10C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged with an internal switch. The device doesn't restart until the junction temperature goes down to 120C and, in any case, until the voltage at the soft-start pin reaches 500mV.
16/24
L6731B
Device description
5.11
Minimum on-time (TON, MIN)
The device can manage minimum on-times lower than 100ns. This feature comes down from the control topology and from the particular over-current-protection system of the L6731B. In fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6731B, neither for the over-current protection, given that during the off-time the valley-current-protection can operate in every case. The first advantage related to this feature is the possibility to realize extremely low conversion ratios. Figure 10. shows a conversion from 14V to 0.3V at 500KHz with a TON of about 50ns.
Figure 10. 14V -> 0.3V@500KHz, 5A VOUT
IL
VPHASE
50ns
The on-time is limited by the turn-on and turn-off times of the MOSFETs.
17/24
Application details
L6731B
6
6.1
Application details
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current (IL) between 20% and 30% of the maximum output current. The inductance value can be calculated with the following relationship:
L
Vin - Vout Vout Fsw I L Vin
(2)
Where FSW is the switching frequency, Vin is the input voltage and Vout is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size.
6.2
Output capacitors
The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
Vout ESR = Iout ESR
(3)
Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas:
VoutCOUT =
Iout 2 L 2 Cout (Vin, min D max - Vout )
(4)
VoutCOUT =
Iout 2 L 2 Cout Vout
(5)
Formula (4) is valid in case of positive load transient while the formula (5) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6731D is 100%. For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum Cout value can be set. The ESR and Cout values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula:
Vout = I L ( ESR +
1 ) 8 Cout Fsw
(6)
Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible.
18/24
L6731B
Application details
6.3
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Irms = Iout D (1 - D)
Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The losses in worst case are:
P = ESR (0.5 Iout ) 2
6.4
Compensation network
The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulsewidth modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/ VCOMP. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC.
Figure 11. Compensation Network
19/24
Application details
L6731B
The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade slope and a phase margin greater than 45. To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
LC =
1 L Cout
(13)
ESR =
1 ESR Cout
(14)
Compensation network singularity frequencies:
P1 =
1 (15) C18 C19 R5 C +C 19 18
P 2 =
1 R4 C20
(16)
Z 1 =
1 R5 C19
(17)
Z 2 =
1 C20 (R3 + R4 )
(18)
Compensation network design: - Put the gain R5/R3 in order to obtain the desired converter bandwidth
C =
- - - - -
R5 Vin LC (19) R3 Vosc
Place before the output filter resonance ; Z1 LC Place at the output filter resonance ; Z2 LC Place at the output capacitor ESR zero ; P1 ESR Place at one half of the switching frequency; P2 Check the loop gain considering the error amplifier open loop gain.
Figure 12. Asymptotic Bode plot of Converter's open loop gain
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L6731B
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
L6731B
Table 6.
DIM.
HTSSOP16 mechanical data
mm. MIN. TYP MAX. 1.2 0.15 0.8 0.19 0.09 4.9 1.7 6.2 4.3 1.5 0.65 0 0.45 0.60 8 0.75 0 0.018 0.024 6.4 4.4 6.6 4.5 5 1 1.05 0.30 0.20 5.1 0.031 0.007 0.004 0.193 0.067 0.244 0.169 0.059 0.0256 8 0.030 0.252 0.173 0.260 0.177 0.197 0.004 0.039 MIN. inch TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201
A A1 A2 b c D D1 E E1 E2 e K L
Figure 13. Package dimensions
7419276A
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L6731B
Revision history
8
Revision history
Table 7.
Date 22-Dec-2005 31-May-2006 26-Jun-2006
Revision history
Revision 1 2 3 Initial release New template, thermal data updated Note page 5 deleted Changes
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L6731B
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